1. Field of the Invention
The invention relates to a design apparatus, a design method, and a program, and is suitable for use in, for example, a design apparatus and a design method for designing a LSI (Large Scale Integration) logical circuit used in a storage apparatus.
2. Description of Related Art
The design of an LSI logical circuit has been conventionally conducted based on abstractness of RTL (Register Transfer Level) and by using a state transition diagram for performing data flow control. RTL indicates the abstractness for LSI design. Data flow is described on a register-register basis. For the RTL description, HDL (Hardware Description Language) with low abstractness such as VHDL (VHSIC Hardware Description Language) or Verilog-HDL is employed. The HDL source codes described at RTL are then converted into a circuit diagram called a net list, on which IC (Integrated Circuit) cells are connected to one another, by using software called a logic synthesis tool.
In the above-described LSI design work using the state transition diagram, the states of the transition flow need to be manually examined one by one after the formation of the state transition diagram. In the case of a high-performance LSI for a storage apparatus, the states and conditions of a state machine, which are described in a state transition diagram (FSM: Finite State Machine), increase in number because of complicated data flow specifications. Therefore, in such LSI design work, the design quality is easily reduced due to examination failures regarding the state transition flow, bug incorporation, or the like, leading to the problem of an increase in “loss” costs due to LSI reproduction.
Meanwhile, in recent years, a method of raising abstractness from the RTL to a behavior level where an action is extracted for each command (see, e.g., JP2007-042085 A) has been introduced for the purpose of improving quality and productivity. In LSI design using the behavior level, commands are described by using a high-level language such as the C language or System C (extended C language). The commands described at the behavior level are then converted into HDL source codes described at RTL by using software called a high-level synthesis tool, and the source codes are converted into a net list (circuit diagram) by using a logic synthesis tool.
Incidentally, high-level synthesis used for behavior-level design has had a problem (first problem) that a data path circuit is created for each command, leading to larger circuit scale and higher cost compared with a conventional RTL-based setting method. The high-level synthesis also has had a problem (second problem) that circuit resource sharing is mechanically conducted, not allowing practical resource sharing control, in which control system resources and data system resources are separated from each other, to occur.
In a general high-level synthetic algorithm, a pair of a state machine and a data path is created for one behavior (flow of a series of steps in hardware). In high-level synthesis processing, resource sharing is conducted in a data path, and therefore, a circuit scale can be reduced compared with the conventional design method with respect to one command.
However, regarding the first problem, resource sharing cannot be conducted over plural pairs of state machines and data paths in conventional high-level synthesis processing, and therefore, data path circuits are created corresponding to the increase in the number of commands. An LSI for a computer typified by a storage apparatus has a feature where plural orders are executed on a single data path, and accordingly, has been inadequate for high-level synthesis in terms of circuit scale and cost.
Regarding the second problem, in general logic design, logic circuits for conducting control such as a counter circuit and a comparator are regarded as control system resources, and logic circuits specialized for data transfer such as a data register, an address resister, and a data calculator are regarded as data system resources; and the control system resources and the data system resources are separated during design. This is because the separation of the control system resources and the data system resources enhances the readability and serviceability in circuit configuration so that control is not involved in failures such as a data error. There is also the reason that control system logic consists of a relatively small circuit, leading to a low circuit scale reduction effect in resource sharing.
Meanwhile, in high-level processing, parts other than state machines are mechanically subjected to resource sharing, and therefore, a circuit in which control system resources and data system resources are mixed is created. This presents a problem in that the RTL created through high-level synthesis is inferior to the RTL created by a conventional RTL design method in terms of readability or serviceability, or circuit quality.